The present invention relates to a method for fabricating a power device, and more particularly, to a method for fabricating a trench power device by forming an oxide layer at the bottom of a trench.
U.S. Pat. No. 6,437,386 to Hurst et al., the entirety of which is fully incorporated by reference herein, discloses total gate charge as an important parameter in a trench power MOSFET. In some applications of conventional trench power MOSFETs, such as DC-DC converters, the lower the gate charge the better is the efficiency of the overall design. One major component of the total gate charge is the charge required to supply what is known as the Miller capacitance.
The Miller capacitance is a parasitic capacitance that forms between the gate and the drain. The Miller capacitance is an effective increase of the gate to drain capacitance effect due to a rising drain current in the MOSFET active state. As a result, a higher proportion of the total gate charge flows through the gate-drain capacitance, and the rate of the rise of the gate to drain voltage is reduced. Thus, an effective way to lower the gate charge is to reduce the Miller capacitance. One method to decrease the Miller capacitance is to increase the thickness of the gate dielectric. A uniformly thicker gate dielectric layer, however, requires higher gate charge which results in lower efficiency.
Accordingly, there is a need for an improved process for fabricating a trench power device that can prevent the aforementioned RC delay problem due to the Miller capacitance.